Non-volatile memory (NVM) arrays, such as erasable, programmable read only memory (EPROM) or flash memory arrays, or electrically erasable, programmable read only memory (EEPROM) arrays, require high positive or negative voltages to program and erase memory cells of the array.
Read and write operations are typically carried out with voltages that are regulated above a positive voltage supply Vdd. The circuitry that supplies and controls the programming and verification voltages generally comprises a high voltage regulator or high voltage pump (the terms being used herein interchangeably). A typical high voltage regulator architecture is shown in FIG. 1.
A current mirror including a pair of PMOS (p-channel metal oxide semiconductor) transistors 4 and 5 have their gates connected to each other and their sources connected to a high voltage supply Vhv—supply. The gate of transistor 4 is connected to its drain. The current through transistor 4 is I1 and the current through transistor 5 is I2. The drain of transistor 5 is connected via a node n to Vout and to a divider 6 comprising a pair of serially connected circuit elements B1 and B2, e.g., resistors, diodes or capacitors. Divider 6 passes a feedback voltage fb to one of the inputs of a voltage amplifier (also called a differential stage or differential amplifier) 7. Differential amplifier 7 receives an input reference voltage Vref at one of its other inputs, and is also connected to positive voltage supply Vdd. The output of differential amplifier 7 may be connected to the gate of an NMOS (n-channel metal oxide semiconductor) transistor M. The drain of transistor M is connected to the drain of transistor 4, and the source of transistor M is connected to ground.
The open loop gain (Gloop) of the high voltage regulator of FIG. 1 (i.e., the ratio of the output voltage to the differential input voltage without any external feedback) is given by:Loop Gain=Gloop=Gdivider*GDA*GNMOS*m 
wherein m is the ratio of the two currents I1 and I2, that is, I2=mI1 
The feedback voltage Vfb is approximately equal to the reference voltage Vref (Vfb≈Vref)
In the case of divider 6 comprising a pair of serially connected resistors, the following relations hold:ΔVfb=Gdivider*ΔVout=(RB1+RB2)/RB2*ΔVout Vout=(RB1+RB2)/RB2*Vfb≈(RB1+RB2)/RB2*Vref 
There is an inherent stability problem with the prior art voltage regulator of FIG. 1, because a high loop gain (although having a fast recovery time) leads to instability of the regulator. On the other hand, a low loop gain results in a slow recovery time. In the case of a resistor divider, there may be a problem of parasitic capacitance to ground of the resistors, leading to another stability/recovery time problem. An additional capacitor divider problem is that of parasitic capacitance to ground which adversely affects the accuracy of Vout. An additional diode divider problem is that it is not possible to have an arbitrary Vout without significantly changing I2.